Self-timed circuit techniques, which were once thought of only as research-oriented projects, are quickly becoming mainstream in VLSI (Very Large Scale Integration) circuitry applications. Self-timed circuits require no clocks for operation as do traditional systems. Self-timed circuits operate asynchronously on the simple concept of demand. That is, a self-timed circuit operates only when asked to, generates necessary outputs according to its own internal scheduling and presents the results to the requester. After performing its task, the self-timed circuit "goes to sleep" and awaits the next instruction or request. While in the sleep condition, no power is dissipated since no operation is taking place. This is contrary to traditional synchronous systems where even when a circuit is not needed, there is at least power dissipated by the clock circuitry running through the system. That idle power can be significant. Studies show that clocking power is approximately 30% of the overall power on a given VLSI circuit/chip. Consequently, self-timed circuits have at least a power advantage over traditional circuits.
Self-timed circuits also have significant advantages over other techniques such as so-called "self-resetting" circuits. Self-resetting circuits require no interaction between driving and receiving circuitry and create scheduling and arrival time conflicts and complications.
FIG. 1 shows an example of a self-timed logic unit 100 including a "circuit pipeline" of four self-timed logic circuits 101, 103, 105 and 107, respectively. In FIG. 1, each block within a self-timed logical unit 100 is labeled as a "Self-Timed Logic Circuit", and can itself be a combination of additional self-timed logic circuits. In operation, the input source or sources indicate to the self-timed logic unit 100 by asserting a request signal REQ and enabling data inputs (for example from a bus or multiple of bus signals) to the first self-timed logic circuit 101. The number of sources is shown as one for simplicity although the number of sources is not limited to one. The first Self-Timed Logic Circuit 101, notes that a request has been made and returns the acknowledge signal ACK to the source(s).
This signifies to the sources that the information on the data bus(es) has been received. The logic that drives the source signals is now free to de-assert the inputs and do other operations, etc., since the first self-timed logic circuit 101 has received the input information and has begun operating with that information.
The first self-timed logic circuit 101 operates on the data and produces a valid output signal 102 to a second self-timed logic circuit 103 and a third self-timed logic circuit 105, respectively, along with data results 106, from the operation of circuit 101. Circuit B 103 and C 105 receive the data or information and send "Complete" signals back along lines 110 and 112 to the first circuit 101 to signify capture of the incoming information. The first circuit 101 is now free to de-assert the output information, and, if necessary, receive further inputs from the input sources for the logical unit shown in FIG. 1.
In a similar manner, the second and third logic circuits 103 and 105 operate on the input information or data such circuits receive and produce a valid output signal and data results which are then sent to a fourth self-timed logic circuit "D" 107 in the present example. The fourth circuit 107 awaits for both "valid" signals to arrive from the second and third circuits 103 and 105, respectively, and then returns a "complete" signal back to the second and third circuits 103 and 105, respectively. The second and third circuits 103 and 105 are now able to de-assert their respective outputs and receive further information as necessary from the first self-timed logic circuit 101. The fourth circuit 107 operates on the information received and produces a "valid" output signal and associated data to an external sink (not shown) in the overall chip design. It is noted that sinks may be single or multiple depending on the particular architecture and placement of a self-timed logical unit. When the receiving units signify that the information has been received (by the assertion of the "completion" signals from sinks), the fourth self-timed logic circuit 107 may de-assert its outputs and receive further information from the second and third self-timed logic circuits 103 and 105, respectively. To control the above described operation, a circuit such as the control circuit shown in U.S. Pat. No. 5,565,798 may be used. U.S. Pat. No. 5,565,798 is hereby included herein by reference.
As a result of the above-described operation, it can be seen that in the general self-timed circuit, no registers are required. In a completely self-timed system, the combination of valid/complete cycles removes the necessity of synchronization of internal units and sub-blocks, as the units time and clock themselves. Holding registers normally used to hold data for synchronization with other functions would therefore be not required in a fully self-timed system. Self-timed circuits and systems actually synchronize themselves. Therefore in the limit, a completely self-timed microprocessor, for example, would require no on-chip or off-chip clocks.
However, there is a potential penalty associated with self-timed circuitry, i.e. at times a self-timed circuit must wait for a loop to complete before a new operation can begin. Also, a self-timed circuit may be forced to wait for the "valid" signal to arrive, which is typically slightly later than the arrival of the data associated with that "valid" signal. Consequently, using the self-timed approach removes the timing hazards associated with the self-resetting approach, but can come at a cost of some performance, mainly due to latency issues.
Accordingly, there is a need for an enhanced method and apparatus which is effective to provide improved performance from self-timed circuits by avoiding the latency which may be inherent in such circuits.